The design of an integrated circuit typically includes, among other aspects, functional verification and power analysis. Functional verification refers to a practice of testing the circuit and analyzing the results of the test to determine whether the circuit is performing to specification. For example, given a set of inputs, does the circuit generate the expected output? Functional verification can be executed with a relatively large degree of automation to cover all of the various operation conditions of the circuit. Briefly, functional verification ensures that the logical design of the circuit is correct.
In contrast, power analysis is an aspect of circuit design that is directed to the physical requirements of the design specification. Therefore, power analysis is generally performed separately from functional verification, and the tools for power analysis are different from the tools for functional verification.
Conventional power analysis can report power consumption of each cell and activity in each net of a design, given a design and netlist activity file. However, these power reports do not indicate whether the power consumption of a cell is correlated to the functional workload of the cell. In practice, a cell may be consuming power but not producing useful work. In this case, conventional power analysis would not indicate whether power consumption could be reduced.
It is desirable to obviate or mitigate these shortcomings of conventional power analysis.